Stability analysis of different dual-port SRAM cells in deep submicron region using N-Curve Method

Abstract

In this paper, different dual-port SRAM cell structures have been analysed in deep submicron regions. Dual port cells have different ports for read and write operations. Two 9 transistor and two 10 transistor SRAM cells have been evaluated using the N-Curve Method. This method provides better analysis than the traditionally used Butterfly Curve method in submicron regions. The performance evaluation in this paper also includes Leakage Current, Cell Standby Current, Read Current and Data Retention Voltage (DRV). The SRAM cell simulations are performed on 22 nm, 32 nm and 45 nm CMOS technology nodes. All SRAM cells showed moderately desirable parameters, with each cell displaying a performance edge in a certain niche. However, the 9T SRAM cell with supply feedback provided considerably good performance parameters across all technology nodes, exhibiting the highest noise margins, lowest leakage currents, lowest data retention voltage and the lowest read currents.