FPGA –based Optimized Design of Montgomery Modular Multiplier using Karatsuba Algorithm

Abstract

Better area and delay performance is the goal of the modulo multiplier architecture that has been created in this paper. The design's architecture increases both the maximum frequency and the area that is occupied on the intended FPGA. Lightweight elliptic curve encryption is constructed using the suggested architecture as a modular multiplier over general G(p). In this design, radix-2 Montgomery Modular Multiplication structure is enhanced. In order to decrease the critical route latency and raise the maximum frequency, the suggested architecture does not perform subtraction or multiplication operations, instead it performs only one pre-calculated addition operation, which reduces the loops of process in computing. When compared to other state-of-the-art modular multipliers, these multipliers' accuracy is equivalent with better area and delay.