{"title":"Phase factor combination scheme based on pipeline in time domain IP-PTS for PAPR reduction of OFDM systems","authors":"Jinxiang Wang, Xin-chun Wu, Zhigang Mao, Bin Zhou","doi":"10.1109/APCC.2009.5375659","DOIUrl":null,"url":null,"abstract":"Time domain interleaved partitioning partial transmit sequence method (TD-IP-PTS) needs only one inverse fast Fourier transform (IFFT) to reduce peak-to-average power ratio (PAPR) of orthogonal frequency division multiplexing (OFDM) system. However, for one long OFDM symbol, it will need waiting time and many registers to implement the combination of phase factor in TD-IP-PTS. Therefore, the speed of data processing may be lowered and hardware complexity still is higher. In order to improve this problem, we analyze the combination process of phase factor in TD-IP-PTS and find the characteristic of combination. Moreover, this paper proposes a pipeline scheme to implement the combination of phase factor in TD-IP-PTS, which requires only 16 registers and doesn't need waiting time.","PeriodicalId":217893,"journal":{"name":"2009 15th Asia-Pacific Conference on Communications","volume":"67 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 15th Asia-Pacific Conference on Communications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APCC.2009.5375659","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
Time domain interleaved partitioning partial transmit sequence method (TD-IP-PTS) needs only one inverse fast Fourier transform (IFFT) to reduce peak-to-average power ratio (PAPR) of orthogonal frequency division multiplexing (OFDM) system. However, for one long OFDM symbol, it will need waiting time and many registers to implement the combination of phase factor in TD-IP-PTS. Therefore, the speed of data processing may be lowered and hardware complexity still is higher. In order to improve this problem, we analyze the combination process of phase factor in TD-IP-PTS and find the characteristic of combination. Moreover, this paper proposes a pipeline scheme to implement the combination of phase factor in TD-IP-PTS, which requires only 16 registers and doesn't need waiting time.