Integrating Formal Timing Analysis in the Real-Time Software Development Process

R. Henia, L. Rioux, Nicolas Sordon, G. Garcia, Marco Panunzio
{"title":"Integrating Formal Timing Analysis in the Real-Time Software Development Process","authors":"R. Henia, L. Rioux, Nicolas Sordon, G. Garcia, Marco Panunzio","doi":"10.1145/2693561.2693562","DOIUrl":null,"url":null,"abstract":"When designing complex real-time software, it is very difficult to predict how design decisions may impact the system timing behavior. Usually, the industrial practices rely on the subjective judgment of experienced software architects and developers. This is however risky since eventual timing errors are only detected after implementation and integration, when the software execution can be tested on system level, under realistic conditions. At this stage, timing errors may be very costly and time consuming to correct. Therefore, to overcome this problem we need an efficient, reliable and automated timing estimation method applicable already at early design stages and continuing throughout the whole development cycle. Formal timing analysis appears at first sight to be the adequate candidate for this purpose. However, its use in the industry is conditioned by a smooth and seamless integration in the software development process. This is not an easy task due to the semantic mismatches between the design and analysis models but also due to the missing link between the analysis and the testing phase after code implementation. In this paper, we present a timing analysis framework we developed in the context of the industrial design of satellite on-board software, allowing an early integration and full automation of formal timing verification activities in the development process of real-time embedded software, as a mean to decrease the design time and reduce the risks of costly timing failures.","PeriodicalId":235512,"journal":{"name":"Workshop on Software and Performance","volume":"90 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-01-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Workshop on Software and Performance","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/2693561.2693562","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7

Abstract

When designing complex real-time software, it is very difficult to predict how design decisions may impact the system timing behavior. Usually, the industrial practices rely on the subjective judgment of experienced software architects and developers. This is however risky since eventual timing errors are only detected after implementation and integration, when the software execution can be tested on system level, under realistic conditions. At this stage, timing errors may be very costly and time consuming to correct. Therefore, to overcome this problem we need an efficient, reliable and automated timing estimation method applicable already at early design stages and continuing throughout the whole development cycle. Formal timing analysis appears at first sight to be the adequate candidate for this purpose. However, its use in the industry is conditioned by a smooth and seamless integration in the software development process. This is not an easy task due to the semantic mismatches between the design and analysis models but also due to the missing link between the analysis and the testing phase after code implementation. In this paper, we present a timing analysis framework we developed in the context of the industrial design of satellite on-board software, allowing an early integration and full automation of formal timing verification activities in the development process of real-time embedded software, as a mean to decrease the design time and reduce the risks of costly timing failures.
在实时软件开发过程中集成形式化时序分析
在设计复杂的实时软件时,很难预测设计决策如何影响系统时序行为。通常,工业实践依赖于经验丰富的软件架构师和开发人员的主观判断。然而,这是有风险的,因为只有在实现和集成之后才能检测到最终的定时错误,此时软件执行可以在系统级别上在实际条件下进行测试。在这个阶段,纠正计时错误可能非常昂贵和耗时。因此,为了克服这个问题,我们需要一种有效、可靠和自动化的时间估计方法,这种方法已经适用于早期设计阶段,并持续贯穿整个开发周期。乍一看,正式的时间分析似乎是这一目的的适当候选者。然而,它在行业中的使用是由软件开发过程中的平滑和无缝集成所决定的。由于设计和分析模型之间的语义不匹配,而且由于代码实现后的分析和测试阶段之间缺少链接,这不是一项容易的任务。在本文中,我们提出了我们在卫星星载软件工业设计背景下开发的时序分析框架,允许在实时嵌入式软件开发过程中早期集成和完全自动化正式时序验证活动,作为减少设计时间和降低代价高昂的时序故障风险的一种手段。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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