Increasing the Accuracy of Reliability-aware Resynthesis with Standard Cell Reliability Characterization

Abstract

The article proposes a method for improving the reliability-aware resynthesis flow of combinational logic circuits. It is proposed to use information about library cells schematics, thereby partially taking into account the electrical masking mechanism. The method involves preliminary characterization of the entire library for the probability of cell failure. It is assumed that cells are exposed to radiation and are subject to impact of heavy charged particles. Characterization is done through SPICE simulations and can take into account different operating conditions and different types of influences. This process takes place once for the entire library, and only the obtained tabular data is used in resynthesis process. Experiments show that resynthesis results can be improved by taking into account the transistor structure of the library cells and the distribution of signals at the inputs of the elements with no runtime increase. It has been shown that, without considering an electrical masking at the level of distinct cells, the results of resynthesis flow are too optimistic.