A system level performance model for asynchronous micropipeline circuits

Abstract

In this paper we present how an asynchronous system, using micropipelines, can be modelled in a system level performance model. We have introduced structures for pipeline stages and feedback structures. The model has been used in order to find out at what complexity a micropipeline implementation can out-perform a synchronous one. We have also used it for examining if micropipelines can be used as an alternative to clock-gating as a method for saving power. Results from these simulations are presented and compared to measurements on a complex asynchronous circuit.