HDL Code Optimizations: Impact on Hardware Implementations and CAD Tools

Abstract

With the dramatic increase in utilization of FPGAs for hardware designs in various application domains, CAD tools play a vital role in the development and implementation of FPGA-based designs. Although CAD tools are typically designed to optimize FPGA-based designs to enhance certain performance metrics during the synthesis-to-implementation process, in this work, we illustrate that CAD tools are susceptible to HDL coding style; thus, minor difference in HDL constructs/codes, lead to significantly different final hardware implementations, which in turn impacts the area-efficiency and speed-performance. By utilizing simple hardware circuitry, we analyze and demonstrate the impact of "code optimizations", i.e., how the "code optimizations" (i.e., varying HDL constructs/codes) impact the way the FPGA-based CAD tools, and their associated algorithms/techniques, interpret and implement the final hardware circuitry on the FPGA. Our experimental results and analysis ascertain that by performing minor modifications to the HDL constructs/codes (with minor "code optimizations"), we can significantly enhance certain performance metrics of the corresponding hardware implementations in terms of area-efficiency and speed-performance, without changing the underlying hardware circuitry.