Fault simulation on reconfigurable hardware

Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186) Pub Date : 1997-04-16 DOI:10.1109/FPGA.1997.624618

M. Abramovici, P. R. Menon

引用次数: 28

Abstract

The authors introduce a new approach to fault simulation, using reconfigurable hardware to implement a critical path tracing algorithm. The performance estimate shows that the approach is at least on order of magnitude faster than serial fault emulation used in prior work.

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可重构硬件的故障仿真

作者介绍了一种新的故障仿真方法，利用可重构硬件实现关键路径跟踪算法。性能估计表明，该方法比先前工作中使用的串行故障仿真至少快一个数量级。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186)

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