Investigating Cache Energy Efficiency in Multimedia Processors

Abstract

In this work we study how cache complexity impacts energy and performance in multimedia processors. We estimate cache energy budget for a multimedia processor similar to Intel's XScale and calculate energy and latency break-even points for realistic and ideal cache organizations. We show that design efforts made to reduce cache miss rate are only justifiable if the associated latency and energy overhead remain below the calculated break-even points. Moreover, we show that, for the applications studied here, the instruction cache has a lower latency break-even point compared to the data cache. However, investing energy in the data cache is likely to result in better energy efficiency compared to the instruction cache. We also study alternative cache configurations and investigate if such alternatives would improve energy-efficiency.