A new technique for noise-tolerant pipelined dynamic digital circuits

Abstract

Noise issues are becoming a main concern in digital systems due to the aggressive scaling trends in devices and interconnections. To address this problem, we present a new noise-tolerant dynamic circuit technique suitable for pipelined dynamic digital circuits. Simulation results for a CMOS AND gate show that the proposed technique has an improvement in the ANTE of 3.4/spl times/ over conventional dynamic logic. The improvement in the delay-ANTE quotient is 2.8/spl times/ over conventional dynamic logic, 2.0/spl times/ over the twin-transistor technique and 1.7/spl times/ over Bobba's technique. A 4-bit full-adder simulated using the proposed technique improves ANTE by 2.1/spl times/ over the conventional dynamic circuit.