Simple evaluation of very low currents in process characterization

Abstract

A test structure dedicated to the evaluation of very low currents for MOS process characterization is presented. The device consists of an amplifier plus a bias voltage set implemented on the chip and connected to the leaky element. The principle is given, and SPICE simulations, based on 2- mu m CMOS industrial technology, show the structure response. Owing to this structure, a strong current amplification is obtained. Consequently, only a classical transistor parameter analyzer is required to evaluate currents in the fA range.<>