The design and analysis of a pipeline stage for use in a multistage analog-to-digital conversion

Abstract

An architecture is proposed to achieve high speed analog-to-digital conversion. This architecture is based on the multi-stage analog-to-digital conversion technique. The multistage method utilizes pipelining to allow concurrent operation of smaller conversion segments. These segments are appended to form a composite result. Through pipelining, a reduction in circuit area is also achieved.