In-Flight Logic Analysis on OPS-SAT

Abstract

Nothing is perfect. Even carefully developed hardware components can sometimes exhibit unexpected behaviour. This is even more likely in harsh environments, like the one satellites are exposed to. However, on satellites hardware analysis is limited to the data obtained by a constrained set of integrated sensors. Therefore, only expected failure cases can be traced, or only indirect monitoring is possible. In this paper, we present an adaptable way to analyse hardware in the field, to solve this problem. Our approach was implemented in-flight on ESA's OPS-SAT satellite, where such an unexplainable fault was noticed. Fortunately, OPS-SAT contains a reconfigurable Field-Programmable Gate Array (FPGA) allowing a logic analyser functionality to be implemented. Thereby, any signal present in the FPGA fabric becomes traceable, including all externally connected ones. Here, we describe the implementation, its deployment and the successful execution on the OPS-SAT satellite. Using the captured traces, we performed an in-depth analysis of the erroneous behaviour. Our understanding is, that this is the first time such a technique has been implemented on a flying spacecraft. We hope to encourage in-field adoption, especially in-space FPGA reconfiguration, to drive future innovation.