A 64Gb/s PAM-4 Digital Equalizer With Tap-Configurable FFE and Partially Unrolled DFE in 28nm CMOS

Abstract

This paper presents a high-performance digital equalizer with four-level pulse amplitude modulation (PAM-4) for 64Gb/$s$ backplane I/Os. The digital equalizer consists of a tap-configurable feed-forward equalizer (FFE) and a partially unrolled decision-feedback equalizer (DFE). The first two post-cursor is covered by DFE and then FFE follows, which can largely reduce the influence of noise and crosstalk. The configurable FFE taps enable better adaption for different kind of channels. In order to optimize the internal algorithm, the look-up table (LUT) is used in both FFE and DFE. And the DFE is unrolled for timing closing using a new architecture introduced in this paper. Fabricated in 28nm CMOS, the digital equalizer operates at 64Gb/s with only 5pJ/bit power consumption at 1V.