Speed Improvement in SRAM Cell Using Transmission Gates

Abstract

All battery-operated devices require primary memory that responds fast. By virtue of its high speed and performance, Static RAM is commonly used as cache memory and main memory in many applications. A major challenge faced in design of SRAM Cells is Read Destruction. This work introduces Transmission Gate Differential 8T (TGD8T) SRAM Cell, in which Transmission Gates are used instead of Pass Transistors in feedback path of the Existing D8T SRAM Cell in order to minimize the voltage drop across the Pass Transistors. This reduces the amount of Read Destruction and accelerates the data transmission. The transmission gates have been implemented using both High Threshold Voltage (HVT) and Low Threshold Voltage (LVT) type MOSFETS. The amount of Read Destruction in TGD8T SRAM Cell is 66.59% lesser than that of the Existing D8T SRAM Cell. Further, the transient analysis of the Read Destruction in the proposed design shows a 29.45 % reduction in the Average Transient Time. The TGD8T SRAM Cell using LVT type MOSFETs offers lesser rise time and a lower voltage drop during data transmission over the model using HVT type MOSFETs. Analysis of Static Noise Margin (SNM) of the proposed cell using N-Curve Method shows 0.13% and 5% increase in current and voltage SNMs respectively showing no compromise in noise immunity when compared to the Existing D8T SRAM Cell. The proposed TGD8T SRAM Cell is implemented in Cadence Virtuoso using gpdk 45 nm technology at a supply voltage of 0.5 V.