A Novel 8.4 GHz, High Speed and Low Power Design of Programmable Divider in 180nm CMOS Technology

Abstract

In this paper, a power efficient and fast divide $- (\div) -$ by $32\vert 33\vert 47\vert 48$ multi – modulus prescaler having operating frequency of 8.4 GHz is proposed using a 0.18$\mu$ m CMOS technology. The proposed design includes a wideband high operating speed and low power $\div -$ by $2\vert 3$ prescaler, improvised $\div -$ by 2 counters, transmission gate-based MUX and logical gates to switch between division ratios $32\vert 33\vert 47\vert 48$. The power consumption of novel design is 0.2368 $\mu W, 0.2287 \mu W, 0.2844 \mu$ W and 0.2785 $\mu$ W during division ratio of 32, 33, 47 and 48, respectively when worked at 0.6 V of power supply. The operating speed of design is improved by 14.2% as compared with the conventional design.