Sangeeta Kumari, A. Verma, S. N, U. Yaragatti, H. Pota
{"title":"Transformer-less Common-Ground Inverter With Reduced Components","authors":"Sangeeta Kumari, A. Verma, S. N, U. Yaragatti, H. Pota","doi":"10.1109/PEDES49360.2020.9379545","DOIUrl":null,"url":null,"abstract":"This paper a proposes a five-level transformer-less inverter based on common-ground-type topology is presented. In the common-ground-type utility neutral is directly tied with negative terminal of dc source, leads to the short-circuiting of PV-to-ground parasitic capacitance. Hence it solves variable common mode voltage and leakage current issues. Additionally, this topology has the inherent voltage boosting ability based on the principle of switched/auxiliary capacitor. A simplified logic gate-based PWM strategy and control algorithm is developed to maintain the voltage across auxiliary capacitor. A laboratory prototype is developed which proves the feasibility and merits of proposed inverter topology are presented.","PeriodicalId":124226,"journal":{"name":"2020 IEEE International Conference on Power Electronics, Drives and Energy Systems (PEDES)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE International Conference on Power Electronics, Drives and Energy Systems (PEDES)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/PEDES49360.2020.9379545","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
This paper a proposes a five-level transformer-less inverter based on common-ground-type topology is presented. In the common-ground-type utility neutral is directly tied with negative terminal of dc source, leads to the short-circuiting of PV-to-ground parasitic capacitance. Hence it solves variable common mode voltage and leakage current issues. Additionally, this topology has the inherent voltage boosting ability based on the principle of switched/auxiliary capacitor. A simplified logic gate-based PWM strategy and control algorithm is developed to maintain the voltage across auxiliary capacitor. A laboratory prototype is developed which proves the feasibility and merits of proposed inverter topology are presented.