1-Bit Comparator Designed by Multithreshold FinFET based Sleep Transistor Technique in 18nm

Abstract

Power efficiency in VLSI circuits can be achieved by using several new logic families which are characterized by complementary CMOS technique. New efficient techniques can be achieved by using both high and low threshold FinFETs in digital circuits. Operation of theses FinFETs can be obtained differently in active and sleep mode as per the logic requirement. In this study, multithreshold technique called sleep transistor technique (STT) has been compared with traditional single threshold technique called complementary FinFET technique (CFT). In STT, high threshold transistor is used as sleep transistors which can be operated differently in active and standby mode. FinFET based comparator design has been implemented by both techniques by taking 18nm foundry base. For comparative parametric analysis, product of power consumption and energy with delay i.e. PDP and EDP have been considered. The analysis depicts that multithreshold technique consumes less power and having higher speed of operation as compared to traditional technique. Also, transient response of STT technique has shown no threshold loss problem, which makes it suitable for cascade operation in low power VLSI circuits.