{"title":"Design of a Wideband Differential LNA Based In CMOS 180 nm Technology","authors":"Kamlesh Joshi, M. Mandal, P. Mandal","doi":"10.1109/IMaRC49196.2021.9714611","DOIUrl":null,"url":null,"abstract":"In this work, a design of a wideband differential low-noise amplifier (LNA) is presented for 5G new radio handset receivers. It is shown that a RC feedback instead of the conventional resistive feedback in common-source topology consumes less dc power, maintains low noise Figure and flat gain over a wide frequency band. Further, use of an inter-stage gm boosting inductor and a parallel LC tank circuit at the input side keep other parameters like linearity, absolute gain, input matching and IIP3 comparable to other designs. As an example, a single stage differential LNA is designed in 180 nm C-MOS technology. The LNA provides a flat gain of 13.6 dB over 1.9-4.5GHz. The input reflection remains below -10dB, noise Figure below 2.9dB, reverse isolation over 41 dB over the whole bandwidth. While overall DC power consumption is 10.5mW and IIP3 is -2.5dBm.","PeriodicalId":226787,"journal":{"name":"2021 IEEE MTT-S International Microwave and RF Conference (IMARC)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2021-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE MTT-S International Microwave and RF Conference (IMARC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IMaRC49196.2021.9714611","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In this work, a design of a wideband differential low-noise amplifier (LNA) is presented for 5G new radio handset receivers. It is shown that a RC feedback instead of the conventional resistive feedback in common-source topology consumes less dc power, maintains low noise Figure and flat gain over a wide frequency band. Further, use of an inter-stage gm boosting inductor and a parallel LC tank circuit at the input side keep other parameters like linearity, absolute gain, input matching and IIP3 comparable to other designs. As an example, a single stage differential LNA is designed in 180 nm C-MOS technology. The LNA provides a flat gain of 13.6 dB over 1.9-4.5GHz. The input reflection remains below -10dB, noise Figure below 2.9dB, reverse isolation over 41 dB over the whole bandwidth. While overall DC power consumption is 10.5mW and IIP3 is -2.5dBm.