Analog test bus architecture for small die size and limited pin count devices with internal IPs testability emphasis

Abstract

The crescent complexity of Mixed Signal Integrated Circuits designed for small die size and limited pin count applications in key areas such as embedded applications, introduces a challenge on the IC testability, for debug, production test and field issue control. Traditional analog test approaches based on the existing standards do not completely address the problem due to constraints in architecture complexity, need of dedicated test control interfaces and pin limitations, resulting in expressive test cost impact. This work discuss a cost effective, small die size area Analog Test Bus Interface implemented for small and medium complexity ICs improving its mixed mode interface and reducing the test time. This architecture was implemented in a silicon test vehicle, 0.25u BiCMOS technology, where measurements and results are presented and discussed. An improvement of around 70% in the testability was obtained with this approach, regarding the analog blocks, allowing a powerful real time debug channel.