Limiting the Fault Current of a DFIG Wind Turbine System Using Resistive Ladder Network

Abstract

A doubly fed induction generator (DFIG) is sensitive to grid faults as its stator is directly connected to the grid. DFIG is required to be connected to the grid during grid voltage sag to fulfill the grid code requirements. A resistive ladder fault current limiter (RLFCL) has been proposed for improving the low voltage ride-through (LVRT) capability of the DFIG. The proposed model is designed such that its control change with the change in the bus voltage. The algorithm is developed and simulated in MATLAB. The performance of the proposed model has been compared with that of the conventionally controlled series dynamic braking resistor (SDBR) for different levels of sag in the bus voltage. The simulation results as well as the index-based comparison show that RLFCL performance is superior to SDBR for enhancing the LVRT capability of DFIG. The overall system returns to a steady state within 5 seconds after the clearance of a fault.