Improve timing margins on multi-rank DDR3 RDIMM using read-on die termination sequencing

Abstract

Modern computer systems have large amounts of DRAM running at fast cycle times. JEDEC standards for DDR3 DRAMs set the bounds of operation, but there is significant opportunity for maximizing the operating performance and reliability by optimizing the electrical parameters and the register settings across the many DIMMs in a system. Specifically, it is essential for the system designers to maximize the setup and hold timing margins for robust system operation. In this paper the hold timing of the data bus read operation is investigated. The methodology is presented and applied to setting the On-Die Termination (ODT) start/stop delay settings for optimal operation. The settings are verified by hardware characterization that confirms the updated delay settings improve the timing margin by performing a timing schmoo and observation of the waveforms with a logic analyzer and oscilloscope.