Automatic Cell Layout in the 7nm Era

Pascal Cremer, S. Hougardy, Jan Schneider, Jannik Silvanus
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引用次数: 24

Abstract

Multi patterning technology used in 7nm technology and beyond imposes more and more complex design rules on the layout of cells. The often non local nature of these new design rules is a great challenge not only for human designers but also for existing algorithms. We present a new flow for the automatic cell layout that is able to deal with these challenges by globally optimizing several design objectives simultaneously. Our transistor placement algorithm not only minimizes the total cell area but simultaneously optimizes the routability of the cell and finds a best folding of the transistors. Our routing engine computes a detailed routing of all nets simultaneously. In a first step it computes an electrically correct routing using a mixed integer programming formulation. To improve yield and optimize DFM, additional constraints are added to this model. We present experimental results on current 7nm designs. Our approach allows to compute optimized layouts within a few minutes, even for large complex cells. Our algorithms are currently used for the design of 7nm cells at a leading chip manufacturer where they improved manufacturability and led to reduced turnaround times.
7nm时代的自动单元布局
7nm及以上工艺中采用的多模式技术对电池的布局提出了越来越复杂的设计规则。这些新的设计规则往往是非局部的,这不仅对人类设计师来说是一个巨大的挑战,而且对现有的算法也是一个巨大的挑战。我们提出了一种新的自动单元布局流程,能够通过同时全局优化多个设计目标来应对这些挑战。我们的晶体管放置算法不仅使电池的总面积最小化,同时优化了电池的可达性,并找到了晶体管的最佳折叠方式。我们的路由引擎同时计算所有网络的详细路由。在第一步中,它使用混合整数规划公式计算电正确路由。为了提高产量和优化DFM,在该模型中添加了额外的约束。我们给出了当前7nm设计的实验结果。我们的方法允许在几分钟内计算优化布局,即使是大型复杂的单元。我们的算法目前被一家领先的芯片制造商用于7nm电池的设计,提高了可制造性,缩短了周转时间。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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