Performance Evaluation of Pulse Triggered Flip-Flops in 32 mm CMOS Regime

Abstract

This article summarises the results of considerable research conducted on pulse-triggered flip-flops (P-FFs) with regard to power consumption and delay measurements. These performance metrics are determined for six of the most advanced P-FFs currently available. The flip-flops considered are the clocked pseudo-NMOS level-converting flip-flop (CPN-LCFF), the pulse-generator-free hybrid latch-based flip-flop (PHLFF), the dual dynamic node hybrid flip-flop (DDFF), the cross charge control flip-flop (XCFF), the conditional clock level-converting flip-flop (CC-LCFF), and the single-ended conditional capturing energy recovery (SCCER) flip-flop. The simulations are performed in SPICE using 32 nm CMOS technology. It was observed that SCCER has better power efficiency and DDFF has better speed efficiency at variations in voltage. For wide temperature changes, SCCER again outperformed other designs in power dissipation and DDFF outperformed other designs in terms of speed of operations. Among all the P-FFs, SCCER has the best power delay product (PDP), whereas CPN-LCFF has the worst.