Architecture and Implementation of Power and Area Efficient Receiver Equalization Circuit for High-Speed Serial Data Communication

Abstract

A low power, small area receiver equalizer circuit based on novel threshold multiplexing (TMX) technique is presented. Simulation results based on the proposed sampler circuit and a 3-level 2-tap TMX equalizer circuit implementation show achievable 20~30 ps eye margin improvement for a 5 Gb/s high-speed serial I/O application. This circuit demonstrates a very low PVT sensitivity and extremely wideband operation, which is fully digital and highly scalable and therefore very suitable for SOC applications.