Test effectiveness evaluation through analysis of readily-available tester data

Abstract

Test metrics and fault models continue to evolve to keep up with defect characteristics associated with ever-changing fabrication processes. Understanding the relative effectiveness of current and proposed metrics and models is therefore important for selecting the best mix of methods for achieving a desired level of quality at reasonable cost. Test-metric and fault model evaluation traditionally relies on large, time-consuming silicon-based test experiments. Specifically, tests generated for some specific metric/model are applied to real chips, and unique chip-fail detections are used as relative measures of effectiveness. To reduce the cost of evaluating new test metrics, fault models, DFT techniques, etc., this work proposes a new approach that exploits the readily-available test-measurement data in chip-failure log files. The new approach does not require the generation and application of new patterns but uses analysis results from existing tests. We demonstrate the method by comparing several metrics and models that include: (i) stuck-at, (ii) N-detect, (iii) PAN-detect (physically-aware N-detect), (iv) bridge fault models, and (v) the input pattern fault model (also more recently referred to as the gate-exhaustive metric).