Towards automatic verification of embedded control software

Abstract

The language: sequential function charts (SFC), is a programming and structuring language for programmable logic controllers (PLC). It is defined in the IEC 61131-3 standard and includes various interesting concepts such as parallelism, hierarchy, priorities, and activity manipulation. Although SFCs are perpetually used in the engineering community for programming and the design of embedded control systems, there are hardly any specific verification approaches for them. Existing approaches for Petri nets, Grafcets, or (UML-)Statecharts do not really apply to SFCs, whose structures are similar but include distinct features. We present a method to model-check SFCs. This is done by defining a translation of SFCs into the native language of the Cadence Symbolic Model Verifier (CaSMV). This translation is specifically tailored to cover all the concepts of SFCs and can be performed automatically. Moreover, we demonstrate our approach by an application to a control process in chemical engineering.