An efficient design environment and algorithms for transport processing FPGA

Abstract

We introduce a CAD system for the original FPGA "PROTEUS", which has several features suitable for the efficient realization of practical digital transport processing systems. These features are considered in the design of the CAD system. Our CAD system supports both automatic and manual design environments. The automatic design environment offers complete top down design from high level hardware description to downloading the programming data into the FPGA. In the manual design environment, an interactive chip editor is provided that enables high performance circuits to be constructed skillfully. The paper introduces our design strategy and the algorithms that realize them.