Backside nanotexturing protected by thin silicon layer for high bending strength ICs

Chia-Liang Hsu, Kunal Kashyap, Amarendra Kumar, J. Yeh, M. T. Hou
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Abstract

Backside nanotexturing fabricated by electroless metal assisted wet chemical etching, protected with a deposited thin silicon layer, is a new approach to create high bending strength silicon samples. Bending strength for protected nanotextured samples followed by CMP process was enhanced by ~3.4 folds as compared to polished silicon samples, which emphasize the possibility of industrial implementation. The morphology of silicon deposition layer upon nanotexture influences the stress behavior, which need an adequate fabrication technique for uniform deposition at wafer scale. The thin protection layer upon nanotexture prevents the unwanted particle trapping, which affects the electrical performances of the device. Moreover, this technology provides a rupture resistive solution for IC, MEMS and photovoltaic devices for industrial implementation.
高抗弯强度集成电路的背面纳米织构由薄硅层保护
利用化学金属辅助湿法化学蚀刻技术制备背面纳米织构,并在表面沉积薄硅层,是制备高抗弯强度硅样品的新方法。与抛光硅样品相比,经CMP处理后的保护纳米纹理样品的抗弯强度提高了约3.4倍,这强调了工业化实施的可能性。硅沉积层在纳米结构上的形貌会影响其应力行为,因此需要适当的制备技术才能在晶圆尺度上均匀沉积。纳米结构上的薄保护层防止了不必要的粒子捕获,从而影响了器件的电性能。此外,该技术为工业实施的IC, MEMS和光伏器件提供了抗破裂解决方案。
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