lGb/s Ground Referenced Low Voltage Differential Signal I/O Interface in 0.35μm CMOS

2005 IEEE Conference on Electron Devices and Solid-State Circuits Pub Date : 2005-12-19 DOI:10.1109/EDSSC.2005.1635318

Y. Tiao, Meng-Lieh Sheu, Yen-Po Chen

引用次数: 1

Abstract

This paper presents a circuit design of ground referenced low voltage differential signal (GLVDS) I/O interface operating at 1 Gb/s. A GLVS transmitter /receiver chip is realized by using TSMC 3.3V 0.35μm 2P4M CMOS process, and its core size is 185μm*85μm.

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lGb/s地参考低压差分信号I/O接口在0.35μm CMOS

本文提出了一种工作速度为1gb /s的地基准低压差分信号(GLVDS) I/O接口的电路设计。采用台积电3.3V 0.35μm 2P4M CMOS工艺实现了GLVS收发芯片，其核心尺寸为185μm*85μm。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2005 IEEE Conference on Electron Devices and Solid-State Circuits

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