M. Lapointe, L. Collier, T. Kajiwara, J. Dickens, J. Mankowski, A. Neuber
{"title":"Improving Fast SiC MOSFET Switching Using an Inductive Gate Drive Approach","authors":"M. Lapointe, L. Collier, T. Kajiwara, J. Dickens, J. Mankowski, A. Neuber","doi":"10.1109/PPPS34859.2019.9009986","DOIUrl":null,"url":null,"abstract":"An innovative gating scheme for wide bandgap semiconductor switches is investigated to fully exploit recent advances of SiC MOSFET properties in hold-off voltage (from single digits to tens of kV) and low on-state resistance (tens of mΩ). Robust gate driving techniques are required to achieve fast risetimes on the order of 10–20 ns. Further, due to the high dI/dt, and subsequent inductive kickback, parasitic inductance may drastically affect the performance of commercially available totem-pole gate drivers. Further, traditionally packaged MOSFETs exhibit additional degradation of switching characteristics due to the introduction of parasitics primarily due to their lead geometry.","PeriodicalId":103240,"journal":{"name":"2019 IEEE Pulsed Power & Plasma Science (PPPS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE Pulsed Power & Plasma Science (PPPS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/PPPS34859.2019.9009986","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
An innovative gating scheme for wide bandgap semiconductor switches is investigated to fully exploit recent advances of SiC MOSFET properties in hold-off voltage (from single digits to tens of kV) and low on-state resistance (tens of mΩ). Robust gate driving techniques are required to achieve fast risetimes on the order of 10–20 ns. Further, due to the high dI/dt, and subsequent inductive kickback, parasitic inductance may drastically affect the performance of commercially available totem-pole gate drivers. Further, traditionally packaged MOSFETs exhibit additional degradation of switching characteristics due to the introduction of parasitics primarily due to their lead geometry.