Critical Signature Assertion and On-the-Fly Recovery for Control Flow Errors in Processors

Abstract

This paper presents a highly effective hybrid control flow error (CFE) detection and recovery mechanism for fault-tolerant instruction set processors. The mechanism consists of two innovations: critical signature assertion (CSA) and on-the-fly recovery (OTFR). The proposed mechanism is experimented with a commercial 32-bit microcontroller core, Andes N801s. Compared with related work, our approach achieves up to 75% and 221% lower in memory size and performance overheads respectively, and reduces the error correction latency by up to 54%, at the reasonable costs of 3470 gates (+19%) and 967uW (+17%) power and merely 0.3% sacrifice in fault coverage.