V. Koundinya, Madanu Karun Chand, D. Dhushyanth, Devarajugattu Jayanth Saikumar, Arumalla Varun Sai, Venu Birudu, R. Vaddi
{"title":"Design and Analysis of 4-bit and 5-bit Flash ADC’s in 90nm CMOS Technology for Energy Efficient IoT Applications","authors":"V. Koundinya, Madanu Karun Chand, D. Dhushyanth, Devarajugattu Jayanth Saikumar, Arumalla Varun Sai, Venu Birudu, R. Vaddi","doi":"10.1109/iSES52644.2021.00057","DOIUrl":null,"url":null,"abstract":"Analog-to-Digital Converter (ADC) design plays an important role for accurate and efficient interfacing of real-world signals for IoT platforms embedded with multiple sensors. In this paper, a Flash or direct conversion 4-bit and 5-bit ADCs are designed and implemented in 90nm CMOS. The performance of the flash ADC is evaluated against important performance metrices. The proposed 4-bit ADC achieve a power consumption of 1.41mW, SNR of 26.184dB, 3.71 ENOB and 16.19 pJ/step of FoM and 5-bit ADC achieve a power consumption of 2.921mW, SNR of 31.149dB, 4.51 ENOB and 19.12 pJ/step of FoM.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/iSES52644.2021.00057","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Analog-to-Digital Converter (ADC) design plays an important role for accurate and efficient interfacing of real-world signals for IoT platforms embedded with multiple sensors. In this paper, a Flash or direct conversion 4-bit and 5-bit ADCs are designed and implemented in 90nm CMOS. The performance of the flash ADC is evaluated against important performance metrices. The proposed 4-bit ADC achieve a power consumption of 1.41mW, SNR of 26.184dB, 3.71 ENOB and 16.19 pJ/step of FoM and 5-bit ADC achieve a power consumption of 2.921mW, SNR of 31.149dB, 4.51 ENOB and 19.12 pJ/step of FoM.