A Coarse Grained Reconfigurable Architecture for SHA-2 Acceleration

Abstract

The development of high-speed SHA-2 hardware with high flexibility is urgently needed because SHA-2 functions are widely employed in numerous fields, from loT devices to cryp-to currency. Unfortunately, the existing SHA-2 circuits have difficulty in achieving high flexibility and hardware efficiency. Therefore, this paper proposes a coarse-grained reconfigurable architecture (CGRA) for accelerating SHA-2 computation, named a CGRA SHA-2 accelerator. To effectively support various algorithms and requirements, three optimization techniques are proposed to achieve high flexibility and hardware efficiency. First, an on-demand pro-cessing element array is proposed to enable flexible computation for long and short messages. Second, a dual-ALU processing element (D-PE) is proposed to compute various SHA-2 functions. Third, the pipelined dual-ALU architecture is proposed to reduce the critical paths, leading to remarkably improved performance and hardware efficiency. The accuracy of our proposed accelerator is verified on a real hardware platform (the Xilinx Alveo U280 FPGA). Besides, the experimental results on several FPGAs prove that the proposed CGRA SHA-2 accelerator is significantly higher performance, hardware efficiency, and flexibility than existing works.