Low Cost Recycled FPGA Detection Using Virtual Probe Technique

Abstract

Analyzing aging-induced delay degradations of ring oscillators (ROs) is an effective way to detect recycled fieldprogrammable gate arrays (FPGAs). On the other hand, it requires a large number of measurements of ROs for all FPGAs before shipping, and thus leads to measurement cost inflation. In this research, we propose a low-cost recycled FPGA detection method using a virtual probe (VP) technique based on compressed sensing. The VP technique enables us to accurately predict the spatial process variation on a die from a very small number of sample measurements. Using the estimated process variation as a supervisor, machine-learning algorithm classifies target FPGAs into recycled or fresh. Through experiments using circuit simulation, our method achieves more than 96% detection accuracy using one-class support vector machine where only 20% samples of the frequency are used at the best case. Silicon measurement results on Xilinx Artix-7 FPGAs also demonstrate the efficiencies of the proposed method.