Impact of Load Capacitance and Interface Trap Charges On Dynamic Behaviour of Double-Gate Junctionless Transistor Based CMOS Inverter

Abstract

This research work presents, the dynamic behavior of CMOS inverter designed using n-MOS and p-MOS double-gate junctionless transistors (DG-JLT). Rise time, fall time, propagation delay, and dynamic power dissipation are used to assess the CMOS inverter's performance using ATLAS-3D device simulator. Three-stage ring oscillator is implemented using DG-JLT and its frequency is utilized for propagation delay and dynamic power consumption calculation. Various performance metrics are calculated considering three values of load capacitance (21aF, 31.5aF, and 42aF) to take into account parasitic capacitance and it is observed that with the increase in value of load capacitance from 21aF to 42aF the rise time, fall time, delay and dynamic power consumption increases by 26%,18.18%,16.06%, and 71.70% respectively. In addition, the change in the various parameters of the CMOS inverter because of the presence of two different interface trap charge density profiles is also analyzed. It has been observed that existence of positive charges reduces the load capacitance.