A 138 Mbps jitter based power efficient true random number generator

Dhirendra Kumar, R. Anand, M. Goswami
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引用次数: 1

Abstract

This paper introduces the design and implementation of True Random Number Generator (TRNG) based on clock jitter. The design extracts jitter from asynchronous type ring oscillator for enhanced randomness. The proposed design is implemented by considering 30 ring oscillators (RO) with a high-frequency divider block (designed by T-FF followed by DFF to address setup and hold time problem) and sampling block followed by a shifter. The design utilizes fewer resources yielding hardware redundancy and enhances the level of randomness. This TRNG has been designed and validated using Artix-7 FPGA. Power dissipation and speed have been obtained as 0.5mW and 138 Mbps respectively. The generated random bit stream has also been sampled and converted to a binary format in MATLAB and tested through the DIEHARD statistical test suite for validation. The obtained binary sequences passed all tests successfully.
一个138 Mbps的基于抖动的节能真随机数发生器
介绍了基于时钟抖动的真随机数发生器(TRNG)的设计与实现。该设计从异步型环形振荡器中提取抖动,增强随机性。提出的设计是通过考虑30个环振荡器(RO)实现的,其中有一个高频分频块(由T-FF设计,然后是DFF设计,以解决设置和保持时间问题)和采样块,然后是移位器。该设计利用较少的资源产生硬件冗余,并提高了随机性水平。利用Artix-7 FPGA对该TRNG进行了设计和验证。功耗和速度分别为0.5mW和138 Mbps。生成的随机比特流也被采样并在MATLAB中转换为二进制格式,并通过DIEHARD统计测试套件进行验证。获取的二进制序列成功通过所有测试。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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