Efficient timing analysis for general synchronous and asynchronous circuits

Abstract

After partitioning the circuit into a set of clock groups, an event-driven approach is used to find paths with delays greater than a given threshold value. False paths detected during event propagation are reported to the user. In addition to breaking asynchronous loops dynamically, the tool also checks setup/hold time and minimum pulse width violations in a multiple clock environment. Experimental results are shown to demonstrated the efficiency and effectiveness of the proposed algorithms.<>