A submicron-channel vertical junction field-effect transistor

Abstract

A technique has been devised for fabricating short-channel (<0.5 µm) vertical JFET structures in Si using conventional contact photolithographic techniques. The process utilizes an anisotropic etch followed by a diffusion to form the FET channel. This technique permits fabrication of high-mobility, short-channel devices with low parasitic source resistances. A finite-element numerical simulation of this structure revealed pentode-like common-source output characteristics with moderate transconductance and high saturated output conductance. Deviations of device behavior from that of conventional JFET structures were attributed to depletion spreading in the gate and to carrier accumulation in the channel. Fabrication of the vertical JFET revealed good agreement between observed and predicted behavior. Channel lengths of fabricated JFETs were measured between 0.3 µm and 0.6 µm. FETs with triode-like output characteristics as well as conventional BJTs were fabricated in the same processing sequence simply by incorporating different width source-etch windows in the design.