Parity predict for 34 bit adders with selection

Abstract

The authors consider 34 bit adder parity prediction schemes where the parity is predicted for either the 32 most significant or 32 least significant bits of the final 34 bit adder result, depending on the instruction being executed. Two parity prediction schemes are derived: one that considers the carries into the bytes and one that considers the carries into the nibbles. The two schemes save hardware and logic delay by grouping the adder bits common to both choices, rather than explicitly calculating the parity for the two separate 32 bit results and then choosing between them depending on the instruction performed. The hardware and its associated delay required to implement both parity predictors are of the same order of magnitude as for conventional 32 bit adder parity predictors.<>