Design of hybrid (CSA-CSkA) adder for improvement of propagation delay

Abstract

Adders are the main components in digital designs not only in additions but also in filter designing, multiplexing, and division. The circuit performance depends on the design of base adder. The demand of high-performance VLSI (very large scale integration) systems is increasingly rapidly for used in small and portable devices. The speed of operation is depends on the delay of the basic adder and it is a very important parameter for high performance. There are so many research works have been so far done on the adder to reduce the delay of it. This paper have done comparative study of various parallel adders and proposed a hybrid adder circuit to improve the delay. Carry Save Adder (CSA) and Carry Skip Adder (CSkA) have been incorporated to improve propagation delay. The result shows the effectiveness for propagation delay improvement.