Switching Performance Evaluation of 650 V Vertical GaN Fin JFET

Abstract

This work reports the first switching performance characterization of a 650 V NexGen's Vertical GaNTM fin-channel junction field effect transistor (Fin-JFET) fabricated on 4-inch GaN-on-GaN wafer. Compared to similarly-rated GaN HEMT and SiC MOSFET, the GaN Fin-JFET has smaller specific on-resistance, die size, and output capacitance ($C_{\text{oss}}$). To exploit these merits in switching applications, an RC interface gate driver was selected with the driving strategy optimized by switching transient analysis. In the GaN Fin-JFET, the gate-to-drain capacitance ($C_{\text{GD}}$) dominates $C_{\text{oss}}$. Accordingly, the positive gate driver input voltage ($V_{G}^{+}$) was found to be critical to enable a fast gate charging for the Fin-JFET. Increasing $V_{G}^{+}$ from 8 V to 12 V allowed for a considerable reduction in the fall time and turn-on energy ($E_{\text{ON}}$). Compared to similarly-rated GaN HEMTs and SiC MOSFETs, the vertical GaN Fin-JFET shows smaller turn-off energy ($E_{\text{OFF}}$) and similar $E_{\text{ON}}$, suggesting its good promise for soft switching applications. Finally, a zero-voltage switching converter based on the GaN Fin-JFET half bridge was demonstrated with a switching frequency up to 1 MHz, in which the Fin-JFET's $E_{\text{OFF}}$ was extracted to be 1.7 µJunder the 400 V/6 A switching condition.