VLSI Architecture of 36-Mode Reconfigurable FFT Hardware Chip with Newly-Developed 2D-FIFO Arrangement Structure

Abstract

In this paper, we propose a reconfigurable FFT hardware architecture for 3GPP LTE systems, supporting up to 36 different FFT sizes. It simultaneously includes various mixed- radix combination of radix-2, radix-3, and radix-5 FFT operations in a stand-alone FFT-processing chip. In the main FFT -computing, a novel reconfigurable processing kernel engine is developed to support 4 configuration types of changeable hybrid-radix FFT operations. In the data storage aspect, a newly-developed 2D-FIFO arrangement structure is used to flexibly handle efficient reading and writing data-access for 36 different FFT sizes. In addition to FPGA prototyping design approach, we also provide the ASIC implementation by TSMC 90-nm CMOS technology. The developed FFT chip only has a core area of 1.416 mm2, consuming 24.2 mW and reaching maximum operating frequency of 111.11 MHz in chip.