A. Deyasi, A. R. Chowdhury, Krishnendu Roy, A. Sarkar
{"title":"Effect of High-K Dielectric on Drain Current of ID-DG MOSFET Using Ortiz-Conde Model","authors":"A. Deyasi, A. R. Chowdhury, Krishnendu Roy, A. Sarkar","doi":"10.1109/EDKCON.2018.8770399","DOIUrl":null,"url":null,"abstract":"Drain-to-source current of independently-driven double gate (ID-DG) MOSFET is analytically computed following Ortiz-Conde model in sub 100 nm channel length in presence of different high-K dielectrics. Fowler-Nordheim tunneling concept is invoked due to reduced dielectric thickness; and front gate control is tailored to analyze the effect on current and pinch-off voltage. Excellent agreement is observed with published literatures for high front-gate voltage when device is lightly doped; which speaks in favor of the work within dimensional constraints. Percentage change of current considering body effect is estimated for different gate bias. Result speaks in favor of low power analog applications.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDKCON.2018.8770399","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
Drain-to-source current of independently-driven double gate (ID-DG) MOSFET is analytically computed following Ortiz-Conde model in sub 100 nm channel length in presence of different high-K dielectrics. Fowler-Nordheim tunneling concept is invoked due to reduced dielectric thickness; and front gate control is tailored to analyze the effect on current and pinch-off voltage. Excellent agreement is observed with published literatures for high front-gate voltage when device is lightly doped; which speaks in favor of the work within dimensional constraints. Percentage change of current considering body effect is estimated for different gate bias. Result speaks in favor of low power analog applications.