Correctness of Synthesis for Tree based Decomposed Algorithm in Semiconductor Memory Designs with Larger Decoders

Abstract

The larger decoders are widely used in the row and column circuitaries of semiconductor memories. Indeed, the larger n-to-2n decoder can be designed in the exponential number of possible ways. It is non trivial to find the design with least delay among all possible exponential cases. However, the tree based decomposition algorithm is to find the best among all possible designs in the polynomial time. This larger decoder with least delay can be used to design the semiconductor memory. This paper proves that the tree-based decomposition algorithm is effective in designing larger decoders for semi-conductor memory design using a tree of smaller decoders for a particular CMOS technology library. The experimental result shows that the algorithm helps in achieving an efficient semiconductor memory design made of larger decoders with less delay. For example, 64x64 SRAM memory design using the proposed decoder achieves an improvement of 12.7% in delay compared with a design using 1-to-2 decoder tree for 180-nm CMOS technology.