A 4-bit 6GS/s time-based analog-to-digital converter

Abstract

This paper proposes a 4-bit 6GS/s Time-Based Analog-to-Digital Converter (TADC) to be integrated inside the Software Defined Radio (SDR) receivers. The TADC is mainly composed of two blocks which are the Voltage-to-Time Converter (VTC) and the Time-to-Digital Converter (TDC). A prototype of the proposed TADC is implemented using 65 nm technology with a sampling rate of 6GS/s. An ENOB of 3.68 is achieved for an input frequency of 1.331 GHz. The whole system consumes a total power of 21.4 mW.