Optimized hardware implementation of the advanced encryption standard algorithm

Abstract

Data encryption has become a vital need for protecting the user data in most of communication areas. Advanced Encryption Standard (AES) algorithm has become the optimum choice for various security services in numerous applications due to its reliability and flexibility. The AES algorithm faces two main challenges which included in both encryption/decryption speed, and the consumed implementation area. This paper presents an optimized implementation of the AES algorithm with respect to the consumed implementation area by combining both data and key expansion approaches. The optimized implementation of AES increases its applicability in the small sized devices such as mobile phones and smart cards. The experimental outcomes prove the superiority of the proposed optimization approach compared to the available approaches in the literature with acceptable frequency and throughput for low throughput applications.