Analysis of SRAM cell design: a better perspective for reducing the chip area and power consumption by increasing the stability of SRAM cell

Abstract

In the semiconductor industry, while designing digital system memory section plays a significant role on chip. For a long time now, we have been working on the memory designing but the process needs modifications every year. Initially we are working on designing of CMOS based SRAM, following which we worked on multigate transistor such as design of FinFET based SRAM. Presently we are working on the latter, because with the rise in number of transistors, the on-chip region also increases, which is why we are working on reducing the chip area as well as the power consumption these days. With the technology scaling the size of the transistor is decreased but this will affect instability of SRAM cell. As the technology scaling is done the SRAM cell is operated below threshold region. The major concern with operating SRAM below threshold region is the process variation effects which will cause to transistor mismatch and also degrade the static noise margin.