Current-mode CMOS adders using multiple-valued logic

Abstract

In this paper we report on initial development stages of two designs of current-mode multiple-valued logic (CMMVL) adders utilizing a positive digit (PD) number representation. The first design is the adder cell that uses the radix-2 algorithm and seven levels of current, fabricated in 0.8 /spl mu/m CMOS technology, with a unit current step of 12 /spl mu/A. The second design is a 4-digit decimal adder that uses a standard algorithm for adding decimal numbers represented by 10 current levels, with a unit current step equal to 1 /spl mu/A, fabricated in 1.5 /spl mu/m CMOS technology. The adder requires 4 input terminals compared to 10 terminals necessary for the same function implemented in binary logic.