{"title":"Nano-watt 0.3 V supply resistorless voltage reference with Schottky diode","authors":"V. RenatoCampana, H. Klimach, S. Bampi","doi":"10.1109/LASCAS.2016.7451038","DOIUrl":null,"url":null,"abstract":"The analysis and design of a resistorless sub-bandgap voltage reference using Schottky diode and Low-V<sub>To</sub> transistors is presented herein. The circuit is self-biased and works in the nano-ampere consumption range, achieving full operation at 0.3 V of supply voltage. The design is validated through post-layout simulations including process variability analysis, for a commercial 130 nm CMOS process. A voltage reference of 102.8 mV is reached under V<sub>DD</sub> = 1.2V and 92.5 mV for V<sub>DD</sub> = 0.3V, with a temperature coefficient (TC) of 215.7 ppm/°C and 216 ppm/°C, respectively using curvature correction to improve the TC in the range from -40° C to 120° C. The current consumption is 212 nA with V<sub>DD</sub> = 1.2V at 27°C, and the chip area is 0.0068 mm<sup>2</sup>.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/LASCAS.2016.7451038","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
The analysis and design of a resistorless sub-bandgap voltage reference using Schottky diode and Low-VTo transistors is presented herein. The circuit is self-biased and works in the nano-ampere consumption range, achieving full operation at 0.3 V of supply voltage. The design is validated through post-layout simulations including process variability analysis, for a commercial 130 nm CMOS process. A voltage reference of 102.8 mV is reached under VDD = 1.2V and 92.5 mV for VDD = 0.3V, with a temperature coefficient (TC) of 215.7 ppm/°C and 216 ppm/°C, respectively using curvature correction to improve the TC in the range from -40° C to 120° C. The current consumption is 212 nA with VDD = 1.2V at 27°C, and the chip area is 0.0068 mm2.